The present invention relates generally to leadframes that are parts for assembling a resin mold type of semiconductor devices and more particularly to leadframes used for semiconductor devices needed to operate at high speed and have high heat dissipation. This invention is also directed to electrically conductive plates used with such leadframes and a method for making them.
In general, a resin mold type of semiconductor packages have some advantages of being capable of being mass-produced at low costs and light in weight. When comparing with ceramic packages, however, they offer some serious problems. Among them:
They are poorer in heat dissipation. PA1 They are inferior in electrical properties with respect to noise.
When constructed in a multi-pin configuration, they increase in size with an increase in lead length, resulting in an increase in inductance, interline capacity and so on. Never until now, therefore, have the resin mold type of semiconductor packages been available for semiconductor elements needed to operate at high speed and have high heat dissipation.
In recent years, a sort of package which is a resin mold type of package but nonetheless has the merits of a ceramic package has been proposed in Japanese Provisional Patent Publication No. 63(1988)-246851. This resin mold type of packages makes use of a multi-layer structure of leadframe wherein, as illustrated in FIG. 12, a power source plate 2 built up of a flat metal plate is joined to an inner lead portion 1a of a leadframe body 1 with a laminating adhesive film 3 including adhesive layers 3b and 3b on both sides of a polyimide-based material 3a and an ground plate 5 is additionally joined to the power source plate 2 with the same laminating adhesive film 3.
In that case, the conventional type leadframe 1 is provided, as shown in FIG. 13, for example, with a given number of outer leads 1b electrically connected to an external electric circuit, a given number of inner leads 1a furnished continuous to the outer leads 1b and electrically connected to a plurality of electrodes of a mounted semiconductor element through conductive wires, and a die pad 1c to mount the semiconductor element lead portions 2b and 2b located on the power source plate 2 are connected with the inner lead 1a by press-bending the flat plate. Although not illustrated, the ground plate 5 is likewise provided with lead portions, which are in turn connected with the inner lead 1a. Generally, connection of the power source plate 2 with the inner lead 1a is achieved by electrical resistance welding or laser welding. The junction is now needed to have a minute area with a multi-pin type of leadframe in mind. The above-mentioned problems are solved by using this multi-layer structure of leadframe.
With the conventional multi-layer leadframe set forth in the above-mentioned patent publication, however, difficulty is encountered in keeping the interlayer thermal behavior well-balanced, because a plurality of power source plates are laminated in place with an adhesive-containing polyimide film. This may possibly cause a warp of the leadframe under the influences of heat generated from semiconductor elements and other factors, which may then give rise to package cracking or voids during resin molding.
In most cases, the adhesives on both sides of the polyimide film used must be so after-cured that the reliability of the leadframe can drop due to contamination by outgassing.
Furthermore, when constructed in a multi-pin configuration, leadframes increase in lead length simultaneously with a decrease in lead's sectional areas; the leads are likely to deform as during transportion of the leadframes. To avoid this, a tape 4 for taping purposes, which has an adhesive layer 4b on one side of a linear polyimide-based material 4a as shown in FIG. 13, is generally laid across inner leads 1a of a leadframe 1 and thermally bonded and fixed thereon--called a taping technique, just after the plating step of the production stage of leadframes.
Furthermore, usually applied to multi-pin leadframes made by an etching technique is a so-called "tip-cutting" wherein the lead tips are previously connected to each other with die pads and etching patterns, and they are cut off after taping, thereby preventing deformation of the leads and assuring the flat widths of the leads. Undeniably enough, this contributes to improvements in the yield of multi-pin leadframes produced.
The present applicant has already filed a patent application (Japanese Patent Application No. 1(1989)-253244) for a multi-layer leadframe wherein the region of a leadframe body to be bonded is divided into plural segments to reduce adhesive areas so as to cope with or limit the occurrence of voids or the contamination of the leadframe due to gases outgassing from the adhesive during resin molding.
However, the multi-layer leadframes set forth in this Patent Application No. 1-253244 and the aforesaid Japanese Provisional Patent Publication No. 63-246851 use adhesives in no small quantities; they are all far from providing a complete solution to contamination by outgassing.
A careful choice of adhesives should also be made in consideration of how they transmit thermal influences or loads or how they transmit ultrasonics when they are used, because semiconductor elements and leads are connected together by means of known wire bonding. For this reason, for instance, costly polyimide-based adhesives must be used as the adhesives. In addition, after-cure and incidental steps that are unnecessary steps are often needed, thus making the entire process complicated and incurring cost rises.
Furthermore, conventional leadframes rely upon inexpensive adhesives for the lamination of power source plates as taping adhesives when carrying out the aforesaid taping, which again incur considerable expense and have an adverse influence or reliability.
Still furthermore, for all the aforesaid multi-layer leadframes, die pad-free, exclusively designed leadframe kits should be used to laminate power source plates thereon. For this reason, usual multi-pin, rather than multi-layer, leadframe kits cannot be applied to the aforesaid multi-layer leadframes; they cannot be used to make packages commensurate to high-speed semiconductor elements, resulting in cost increases.